In this project, the student will develop a Digital Down Converter (DDC) on FPGA using Xilinx System Generator tool for Simulink. The purpose is to develop a universal Direct RF Sampling (DRFS) front-end for avionics systems working at VHF/UHF/SHF, e.g. DME, ADSB, XPDR, UAT, VOR, ELT, ILS, etc. The student will program state of the art Software Defined Radio platforms (http://nutaq.com/en/sdr-comparison-chart) using Xilinx Tools ISE Foundation (v13.4) with MATLAB. The systems are already designed and functional using GNU Radio (http://gnuradio.org/) using separate RF front-ends. The student will implement signal down conversion and filtering steps into an FPGA architecture common for all the RF bands. His work needs to be integrated also with related works ongoing within the team framework. RF signal will be digitized using high performance ADCs either as low pass signals for the lower VHF band or using IQ sampling concept for upper bands. Both filtering (and decimation) and down conversion stages will be carried out into an FPGA Virtex-6 using Xilinx DSP for System Generator, instead of in the analog domain. The student will also translate all the avionics systems into the FPGA according to a hybrid FPGA-CPU partitioning strategy optimizing resources. The student will also have the opportunity to test his/her developed system in flight.
Skills required:
- Familiarity with Xilinx Tools
- VHDL
- HIL testing
- Digital signal processing
