According to the schedule, the third Ph.D. student will be in charge of the following tasks:
1) 2-21 Using 1-41 study results, design suitable integrated DRFS architecture
2) 2-22 Study of high performance ADC’s
3) 2-23 Study and design of ADC prototype
4) 2-24 Study and design of integrated aliasing filter
5) 3-40 Characterization and selection of optimal operating sampling rates and frequencies
6) 3-42 DRFS demonstration with both real RF signals and under software control
7) 3-44 Study and analysis of the integration of generic DRFS to SDA in bench tests
8) 4-32 Analysis and evaluation of sensitivity gains
9) 4-33 Evaluation of power consumption under various scenarios
10) 4-34 Estimation of increased reliability benefits from unit(DRFS)
This Ph.D. student starts in the second year of the project to leverage the benefits accrued during the first year of the project. The main objective of this research is to develop an integrated DRFS architecture to work in conjunction with the ISR platform in place of the commercial RFU. In parallel to the discrete DRFS prototyping, the student will have the objective to develop a high speed ADC dedicated to direct RF sampling of the RF signal and integrate such new architecture along with any other necessary receive chain support elements, such as LNA, anti-aliasing filters and amplification. The student will be supported by the post-doctoral fellow and will collaborate with other students working on DRFS in order to achieve the primary goals of:
During the student’s first year (2nd year of the project), this Ph.D. student will focus on the development of the requirements of a high performance ADC in an integrated format for a DRFS sampling receiver chain. Preliminary work will focus on frequency selection, accuracy, phase noise and comparison with the state of the art.Exploiting requirement details garnered from the program’s first year, a short review later-stage aliasing filter requirements, will be done. A high speed ADC architecture model will be developed, suitable for integration on silicon along with the LNA and proper filters. The student will study and implement using proper simulation software, candidate anti-aliasing filters and ADC basic architecture. The work will consist of conceptualization, study, simulate and candidate different methods, architectures and technologies.
In the student’s second year, the LNA, ADC, the control interface and proper filters will be developed and implemented via participation in a multi-project wafer version IC of CMC (Canadian Microelectronic Corporation). Physical layer testing of the preliminary version IC will be undertaken and documented. A study of the linearity and jitter limits will be done with the simulation design software. A first IC prototype will be produce in the second year to further signal analysis. Contributions to the WBR development are expected to take place.
In the student’s third year, the student will focus on understanding and solidifying any outstanding performance and control issues. Once the DRFS IC #1 design has solidified and analysed within the SDR platform, estimates of the decreased power consumption can be made in third year. A second version of the IC will be produced, to improve global performance and robustness. Midway through the student’s third year the IC/evaluation module will be integrated with the complete SDA assembly and bench tested as a complete proof-of-concept DRFS demonstrator. The student is expected to write up detailed findings on the benefits to sensitivity, accuracy, power saving and programmability. The benefits to reliability, robustness, a study of system (phase) noise, and on-the-fly partial reconfiguration activities will be closely monitored and supported by the Ph.D. student. The role of the Ph.D. student is expected to be critical in this power estimation as the RF power is typically the largest power consuming element.
